Hardware Memory Models & Atomic Ordering Semantics

The Illusion of Sequential Consistency

Modern CPUs do not execute instructions strictly in code order. Out-of-Order (OoO) execution engines, store buffers, and invalidation queues reorder loads and stores to maximize pipeline utilization. While x86 enforces Total Store Order (TSO) (loads are not reordered with older loads, stores are not reordered with older stores), ARM64 and Apple Silicon use a weakly ordered memory model where almost any access can be reordered unless constrained by memory fences.

The Five Rust Atomic Orderings

The Acquire-Release Synchronization Pattern

To pass data safely between threads without a mutex, pair a Release store with an Acquire load:

use std::sync::atomic::{AtomicBool, AtomicUsize, Ordering};

static DATA_PAYLOAD: AtomicUsize = AtomicUsize::new(0);
static READY_FLAG: AtomicBool = AtomicBool::new(false);

// Thread 1: Producer
DATA_PAYLOAD.store(42, Ordering::Relaxed);
READY_FLAG.store(true, Ordering::Release); // Releases prior writes to other threads

// Thread 2: Consumer
if READY_FLAG.load(Ordering::Acquire) { // Acquires all writes released by Thread 1
    let val = DATA_PAYLOAD.load(Ordering::Relaxed);
    assert_eq!(val, 42); // Guaranteed to see 42!
}