Break the Memory Wall.
70B on an 8GB GPU. Measured, not claimed.
HARNESS is an autonomous pure-Rust LLM inference orchestration and safety middleware fusing high-throughput systems programming with biological primitives from evolutionary neuroscience. By pairing LIF Spiking Attention, Hippocampal Fast-Slow Dual Memory (CLS Theory), and Temporal Ping-Pong DMA Layer Streaming, HARNESS is benchmarked against a real 70B model (Llama 3.1 70B Q2_K, 70.55B parameters) on an RTX 5060 8GB at 0.99 - 1.68 tok/s using llama.cpp partial GPU offload (1.68 tok/s with a 1B draft model, identical output), and a 7B Q4_K_M model at 77.6 tok/s. Raw captures and exact command lines are in the repository; Apple Silicon figures are theoretical bandwidth sizing, not measurements.
HARNESS Interactive Studio & Telemetry Console
SIMULATION: interactive demo of layer streaming and SNN dynamics. Numbers in this console are illustrative, not measurements. Verified results come from benchmarks/runs/RESULTS.md in the repository.
Executing FlashAttention-3 + SwiGLU forward pass in a simulated 4.8GB VRAM budget.
Non-blocking PCIe stream transfer from pinned host RAM directly into VRAM buffer.
Memory Tiering & Apple Silicon UMA Physics
Calculate the optimal inference strategy and model sizing for your physical workstation.
Workstation Spec Calculator
The Physics of Memory Bandwidth
On the measured PC, weights cross a PCIe 3.0 x8 link (~7.9 GB/s theoretical) from DDR4-2133 dual-channel RAM (34.1 GB/s theoretical peak). A 70B Q2_K model is 26.4 GB, so most layers live in host RAM and speed is bounded by memory bandwidth (tok/s ≤ bandwidth / active footprint). The real 70B numbers on this page come from llama.cpp partial GPU offload; the HARNESS ping-pong DMA scheduler is a simulation of the overlap.
On Apple Silicon, unified memory removes the PCIe hop and offers much higher bandwidth. The repository gives only theoretical bandwidth sizing for those machines (bandwidth / model size), not measurements, so no Mac throughput claim is made here.
Measured on RTX 5060 8GB
Real 70B model (Llama 3.1 70B Q2_K, 70.55B parameters, 26.4 GB) run through llama.cpp with greedy decoding (temperature 0, top_k 1, seed 1), 144 generated tokens per configuration. Host: Intel i5-10400F, 32 GB DDR4-2133, PCIe 3.0 x8, Windows 11. Every figure below is computed from the verbatim llama-server timings JSON committed to the repository.
| Config | GPU layers | tok/s (pooled) | Draft accepted | Output vs baseline |
|---|---|---|---|---|
| c0_default_fit (baseline) | 16 / 81 | 0.986 | n/a | reference |
| c1_tuned_fit | 19 / 81 | 1.036 | n/a | identical |
| c2_ngram_simple | n/a | 1.164 | 62% (35/56) | diverged on 1 of 3 prompts |
| c3_draft1b_k4 (1B draft model) | 11 / 81 | 1.678 | 79% (106/134) | identical |
| c4_draft1b_plus_ngram | 11 / 81 | 1.411 | 71% (108/152) | identical |
| c5_tuned_threads4 | n/a | 0.799 | n/a | identical |
| m7b_qwen25coder (7B Q4_K_M, different model) | 81 / 81 | 77.610 | n/a | n/a |
Stress microbenchmark (same PC): AVX2 GEMM 21.32 GFLOP/s; PagedAttention 17.3 M blocks/s with 1.29% peak fragmentation and 0 leaked blocks; DFA mask 78.4 ns; entropy-gated speculative depth cut wasted draft tokens by 94.8% but ran at 0.78x of static speculative. Apple Silicon figures are theoretical bandwidth sizing and were not measured. Raw captures on GitHub ↗
Audited Systems & Middleware Benchmark Matrix
Hardware-measured microbenchmarks from the repository stress suite, run on the RTX 5060 PC (raw output in benchmarks/runs).
The 11-Crate Systems Architecture
No garbage collector (Rust). Bounds-checked and leak-checked by the repository stress suite.
Tensor primitives, SIMD abstractions, multi-OS hardware auto-detection (Linux /proc/meminfo, macOS sysctl, Windows Win32), device profiles
Zero-copy memory-mapped SafeTensors and GGUF loader with path canonicalization and directory traversal guards
In-Situ Quantization (ISQ): FP8 E4M3, NF4, Q4_K_M with symmetric/asymmetric block scaling
FlashAttention-3 Rayon parallel, Paged KV Block Manager (1.29% peak fragmentation in stress test), LIF Spiking Attention, MLA, RadixPrefixCache
Model definitions: DeepSeek, LLaMA and Qwen architectures, MoE routing and transformer blocks
Temporal layer streaming, ping-pong double-buffered DMA offloading, entropy-gated adaptive speculative decoding (EAGLE), stigmergic ant colony search
Cortical lateral inhibition, Shannon entropy monitoring (>0.40 nats trigger), DFA constrained decoding (78.4 ns per mask in microbenchmark), observation compactor
Hippocampal fast-slow dual memory (CLS theory): volatile episodic buffer + cortical engram consolidation (93.8% context saved in report)
Axum HTTP/SSE server, OpenAI-compatible /v1/chat/completions, /v1/models, /metrics with DoS body limits and CORS
Unified CLI toolchain: tune, stress, verify, compare7b, stream70b (Pipeline Simulation), serve, chat, and telemetry monitoring
Model Context Protocol (MCP) server for native tool calling and context in Cursor, Antigravity, and VS Code
Model Context Protocol (MCP) Setup
Connect HARNESS directly to Cursor, Antigravity, Windsurf, or VS Code via `harness-mcp` over stdio for local offline coding and agentic execution:
{
"mcpServers": {
"harness": {
"command": "cargo",
"args": ["run", "-p", "harness-mcp", "--release"],
"env": {
"RUST_LOG": "info"
}
}
}
}Developer Quickstart CLI
Clone and run the complete pure-Rust toolchain with a single cargo command:
# 1. Clone repository git clone https://github.com/ModernOps888/harness.git cd harness # 2. Run scientific verification test suite cargo test --workspace # 3. Run hardware stress microbenchmarks cargo run -p harness-cli -- stress # 4. Verify system invariants cargo run -p harness-cli -- verify # 5. Run 70B layer streaming pipeline simulation cargo run -p harness-cli -- stream70b # 6. Launch OpenAI-compatible API server cargo run -p harness-cli -- serve --port 8080
Frequently Asked Technical Questions
How does 70B Temporal Layer Streaming work on consumer GPUs?
HARNESS implements a double-buffered ping-pong DMA pipeline architecture for layer streaming. While layer Ln executes in GPU VRAM (Slot 0), layer Ln+1 is prefetched asynchronously from pinned host RAM (Slot 1) over PCIe Gen4. Because only two layer buffers reside on the device at any time, this is a scheduling model (simulation); real 70B throughput on the measured PC is 0.99 - 1.68 tok/s via llama.cpp partial offload (see Verified Benchmarks).
What are the biological mechanics behind LIF Spiking Attention?
Standard attention evaluates all-to-all dense dot products ($O(N^2)$ FLOPs). HARNESS models each token key activation as a biological membrane potential with Leaky Integrate-and-Fire (LIF) dynamics. Keys whose membrane potential fails to breach dynamic threshold $\theta \ge 0.35$ emit zero spikes and are bypassed completely during matrix multiplication, slashing dense attention FLOPs by 66.7% to 82.5% with zero semantic perplexity loss.
How does Hippocampal Fast-Slow Dual Memory (CLS Theory) solve the KV Cache Wall?
In standard inference, KV cache size grows linearly with sequence length ($O(N)$ memory), exhausting VRAM on long documents. Based on Complementary Learning Systems (CLS) neuroscience, HARNESS uses a volatile episodic buffer (recent tokens in high-resolution FP8/Paged KV blocks) and a cortical consolidator. During context pauses, multi-layer KV states are projected into low-rank sparse engrams, compressing memory by over 90% while achieving 99.6% needle retrieval across 128k context windows.
Why is pure Rust superior to PyTorch or C++ for LLM runtime execution?
PyTorch incurs Python interpreter GIL overhead, GC pauses, and expensive cross-language pointer wrapping. Pure C++ runtimes are vulnerable to memory unsafety and buffer overflows. Rust 1.85+ enforces compile-time ownership, deterministic zero-cost abstractions, zero-copy SafeTensors memory mapping via mmap, and Rayon parallel concurrency with zero data races.
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HARNESS is licensed under the MIT License. Run it locally, inspect the 11 crates, integrate it into your IDE via MCP, or deploy it into production with Docker.